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april 2010 doc id 11079 rev 2 1/14 14 STA515W 40-volt, 3-amp, quad power half bridge features ? multipower bcd technology ? low input/output pulse width distortion ? 200 m ? r dson complementary dmos output stage ? cmos-compatible logic inputs ? thermal protection ? thermal warning output ? undervoltage protection ? short-circuit protection description the STA515W is a monolithic quad half-bridge stage in multipower bcd technology. the device can be used as a dual bridge or reconfigured, by connecting pin config to pins vdd, as a single bridge with double-current capability. the device is designed, particularly, to be the output stage of a stereo all-digital high-efficiency amplifier. it is capable of delivering 10 w x 4 channels into 4- ? loads with 10% thd at v cc = 18 v in single-ended configuration. it can also deliver 20 w + 20 w into 8- ? loads with 10% thd at v cc = 18 v in btl configuration or, in single parallel btl configuration, 40 w into a 8- ? load with 10% thd at v cc = 26 v. the input pins have a threshold proportional to the voltage on pin vl. the STA515W comes in a 36-pin powersso package with exposed pad down (epd). powersso36 package with exposed pad down table 1. device summary order code ambient temp. range package packaging STA515W 0 to 70 c powersso36 epd tube STA515W13tr 0 to 70 c powersso36 epd tape and reel www.st.com
introduction STA515W 2/14 doc id 11079 rev 2 1 introduction figure 1. STA515W circuit for quad single-ended amplifiers l11 22 h l12 22 h c51 1 f c71 100nf c91 1 f 1 f 1 f c81 100nf c31 820 f c21 2200 f c58 100nf c58 100nf r57 10k r59 10k r41 20 r61 5k r62 5k r51 6 c53 100nf c60 100nf c61 100nf 15 m3 in1a in1a vl config pwrdn pwr_dn fault tristate thwarn th_warn +3.3v in1b vdd vdd vss vss vccsig vccsig gndreg gndclean in2a in1b in2a in2b protection & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 out1a gnd1a out1a vcc1a 14 12 10 11 out1b gnd1b out1b vcc1b 13 c52 1 f +v cc c62 100nf 7 m17 m15 m16 m14 8 9 out2a gnd2a out2a vcc2a 6 4 2 3 out2b gnd2b d03au1474bc out2b vcc2b 5 19 31 20 gndsub 1 in2b 32 c72 100nf c92 1 f c82 100nf r52 6 c41 330pf r42 20 c42 330pf c32 820 f l13 22 h l14 22 h c73 100nf c93 1 f c83 100nf c33 820 f r43 20 r53 6 c74 100nf c94 1 f c84 100nf r54 6 c43 330pf r44 20 c44 330pf c34 820 f r63 5k r64 5k r65 5k r66 5k r67 5k r68 5k 4 ? 4 ? 4 ? 4 ?
STA515W pin description doc id 11079 rev 2 3/14 2 pin description figure 2. pin out table 2. pin list pin name type description 1 gndsub pwr substrate ground 2, 3 out2b o output half bridge 2b 4 vcc2b pwr positive supply 5 gnd2b pwr negative supply 6 gnd2a pwr negative supply 7 vcc2a pwr positive supply 8, 9 out2a o output half bridge 2a 10, 11 out1b o output half bridge 1b 12 vcc1b pwr positive supply 13 gnd1b pwr negative supply 14 gnd1a pwr negative supply 15 vcc1a pwr positive supply 16, 17 out1a o output half bridge 1a 18 n.c. - no internal connection 19 gndclean pwr logical ground 20 gndreg pwr ground for regulator v dd 21, 22 vdd pwr 5-v regulator referred to ground 23 vl pwr high logical state setting voltage, v l vccsig vccsig vss vss in2b in2a in1b in1a thwarn fault tristate pwrdn config vl vdd vdd gndreg gndclean gndsub out2b out2b vcc2b gnd2b gnd2a vcc2a out2a out2a out1b out1b vcc1b gnd1b gnd1a vcc1a out1a out1a n.c. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 STA515W
pin description STA515W 4/14 doc id 11079 rev 2 24 config i configuration pin: 0: normal operation 1: bridges in parallel, see parallel-output and high-current operation on page 9 25 pwrdn i stand-by pin: 0: low-power mode 1: normal operation 26 tristate i hi-z pin: 0: all power amplifier outputs in high-impedance state 1: normal operation 27 fault o fault pin advisor (open-drain device, needs pull-up resistor): 0: fault detected (short circuit or thermal, for example) 1: normal operation 28 thwarn o thermal-warning advisor (open-drain device, needs pull-up resistor): 0: temperature of the ic >130 o c 1: normal operation 29 in1a i input of half bridge 1a 30 in1b i input of half bridge 1b 31 in2a i input of half bridge 2a 32 in2b i input of half bridge 2b 33, 34 vss pwr 5-v regulator referred to +v cc 35, 36 vccsig pwr signal positive supply table 2. pin list pin name type description
STA515W electrical characteristics doc id 11079 rev 2 5/14 3 electrical characteristics unless otherwise stated, the test conditions for ta bl e 6 below are v l = 3.3 v, v cc = 30 v, r l =8 ? , f sw = 384 khz and t amb = 25 c table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage (pins 4, 7, 12, 15) 40 v v max maximum voltage on pins 23 to 32 5.5 v t op operating temperature range 0 to 70 c p tot power dissipation (tcase = 70 c) 21 w t stg , t j storage and junction temperature -40 to 150 c table 4. recommended operating conditions symbol parameter min typ max unit v cc dc supply voltage (pins 4, 7, 12, 15) 10 - 36 v v l input logic reference 2.7 3.3 5.0 v t amb ambient temperature 0 - 70 c table 5. thermal data symbol parameter min typ max unit t j-case thermal resistance junction to case (thermal pad) - - 1.5 c/w t jsd thermal shut-down junction temperature - 150 - c t warn thermal warning temperature - 130 - c t hsd thermal shut-down hysteresis - 25 - c table 6. electrical characteristics symbol parameter test conditions min typ max unit r dson power p-channel/n-channel mosfet r dson i dd = 1 a - 200 270 m ? i dss power p-channel/n-channel leakage idss v cc = 35 v --50 a g n power p-channel r dson matching i dd = 1 a 95--% g p power n-channel r dson matching i dd = 1 a 95--% dt_s low current dead time (static) see figure 3 - 1020ns
electrical characteristics STA515W 6/14 doc id 11079 rev 2 dt_d high current dead time (dynamic) l = 22 h, c = 470 nf r l = 8 ? , i dd = 3.0 a see figure 4 --50ns t d on turn-on delay time resistive load - - 100 ns t d off turn-off delay time resistive load - - 100 ns t r rise time resistive load see figure 3 --25ns t f fall time resistive load see figure 3 --25ns v cc supply operating voltage - 10 - 36 v v in-low half-bridge input, low level voltage - - - v l / 2 - 300 mv v v in-high half-bridge input, high level voltage - v l / 2 + 300 mv - - v i in-h high level input current v in = v l -1- a i in-l low level input current v in = 0.3 v - 1 - a i pwrdn-h high level pwrdn pin input current v l = 3.3 v - 35 - a v low low logical state voltage (pins pwrdn, tristate) (see ta bl e 7 ) v l = 3.3v --0.8v v high high logical state voltage (pins pwrdn, tristate) (see ta bl e 7 ) v l = 3.3 v 1.7 - - v i vcc- pwrdn supply current from v cc in power down v pwrdn = 0 v --3ma i fault output current on pins fault, thwarn with fault condition v pin = 3.3v -1-ma i vcc-hiz supply current from v cc in 3-state v tristate = 0 v - 22 - ma i vcc supply current from v cc in operation (both channels switching) input pulse width = 50% duty, switching frequency = 384 khz, no lc filters -50-ma i ocp overcurrent protection threshold isc (short circuit current limit) - 36- a v uvp undervoltage protection threshold --7-v t pw_min output minimum pulse width no load 70 - 150 ns table 6. electrical characteristics (continued) symbol parameter test conditions min typ max unit
STA515W electrical characteristics doc id 11079 rev 2 7/14 test circuits figure 3. test circuit figure 4. current dead time test circuit table 7. threshold switching voltage variation with voltage on pin vl voltage on pin vl, v l v low max v high min unit 2.7 0.7 1.5 v 3.3 0.8 1.7 v 5.0 0.85 1.85 v table 8. logic truth table pin tristate inputs as per figure 4 transistors as per figure 4 output mode inxa inxb q1 q2 q3 q4 0 x x off off off off hi z 100offoffonondump 101offononoffnegative 110onoffoffonpositive 111ononoffoffnot used low current dead time = max(dtr,dtf) outxy vcc (3/4)vcc (1/2)vcc (1/4)vcc t dtf dtr duty cycle = 50% inxy outxy gnd +vcc r 8 ? + - vdc = vcc/2 d03au1458 high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=8 ? q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=4.5a iout=4.5a q4 q1 q3 inb d03au1517 ina dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4.5a in the direction shown in figure l68 22 l67 22 outa
applications information STA515W 8/14 doc id 11079 rev 2 4 applications information the STA515W is a dual channel h-bridge that can deliver 20 w per channel into 8 ? with 10% thd at v cc = 18 v with high efficiency. the STA515W converts both ddx and binary-logic-controlled pwm signals into audio power at the load. it includes a logic interface, integrated bridge drivers, high efficiency mosfet outputs and thermal and short-circuit protection circuitry. in ddx mode, two logic-level signals per channel are used to control the high-speed mosfet switches which drive the speaker load in a bridge configuration, according to the damped ternary modulation operation. in binary mode, both full-bridge and half-bridge modes are supported. the STA515W includes overcurrent and thermal protection as well as an undervoltage lockout with automatic recovery. a therma l warning status is also provided. figure 5. block diagram for ddx or binary modes figure 6. block diagram for binary half-bridge mode logic interface and decode the STA515W power outputs are controlled using one or two logic-level timing signals. in order to provide a proper logic interface, pin vl must operate at the same voltage as the ddx control logic supply. logic interface and decode outpl outnl left h-bridge protection circuit regulators outpr outnr right h-bridge inl[1,2] vl pwrdn tristate fault thwarn inr[1,2] outpl left a bridge logic interface and decode protection circuit regulators inl[1,2] vl pwrdn tristate fault thwarn inr[1,2] outnl left b bridge outpr right a bridge outnr right b bridge
STA515W applications information doc id 11079 rev 2 9/14 protection circuits the STA515W includes protection circuitry for overcurrent and thermal overload conditions. a thermal warning pin (thwarn) is activated low (open-drain mosfet) when the ic temperature exceeds 130 c, which is in advance of the thermal shutdown protection. when a fault condition is detected an internal fault signal acts to immediately disable the output power mosfets, placing both h-bridges in the high-impedance state. at the same time an open-drain mosfet connected to pin fault is switched on. there are two possible modes subsequent to activating a fault: z shutdown mode: with pins fault (with pull-up resistor) and tristate independent, an activated fault disables the device, signalling low at pin fault. the device may subsequently be reset to normal operation by toggling pin tristate from high to low and back to high using an external logic signal. z automatic recovery mode: this is shown in the applications circuit in figure 7 and figure 7 on page 10 . pins fault and tristate are shorted toge ther and connected to a time constant circuit comprising r59 and c58. an activated fault forces a reset on pin tristate causing normal operation to resume following a delay determined by the time constant of the circuit. if the fault condition is still present, the circ uit operation continues, repeating until the fault condition is removed. an increase in the time constant of the circuit produces a longer recovery interval. care must be taken in the overall system design so as not to exceed the protection thresholds under normal operation. power outputs the STA515W power and output pins are duplicated to provide a low-impedance path for the device bridged outputs. all duplicated po wer, ground and output pins must be connected for proper operation. pins pwrdn or tristate should be used to set all mosfets to the high-impedance state during power-up and until the logic power supply, vl, has settled. parallel-output and high-current operation when using ddx mode, the STA515W outputs can be connected in parallel to increase the output current capability. in this configuration the devi ce can provide 40 w into 8 ? . this mode of operation is enabled with pin config connected to vdd. the inputs must be combined to give inla = inlb and inra = inrb, then the corresponding outputs can be shorted together to give outla = outlb and outra = outrb. output filter a passive 2nd-order filter is used on the STA515W power outputs to reconstruct an analog audio signal. the system perform ance can be significantly affected by the output filter design and choice of passive components. filter designs for 4- ? and 8- ? loads are shown in the applications circuits of figure 1 on page 2 for the half-bridge mode, and figure 7 and figure 8 on page 10 for the full bridge.
applications information STA515W 10/14 doc id 11079 rev 2 applications circuits figure 7 below shows a typical full-bridge circuit for supplying 20 w + 20 w into 8- ? speakers with 10% thd at v cc = 18 v. figure 7. typical stereo full-bridge configuration for 20 + 20 w figure 8 below shows a single-btl configuration capable of supplying 40 w into a 4- ? load at 10% thd with v cc = 19 v. this result was obtained with peak power for <1 s using the sta308+STA515W+sta50x demo board. a pwm modulator as driver is required. figure 8. typical single-b tl configuration for 40 w l18 22 h l19 22 h c30 1 f c20 100nf c99 100nf c101 100nf c107 100nf c106 100nf c23 470nf c55 1000 f c21 100nf c58 100nf c58 100nf r57 10k r59 10k r63 20 r98 6 r100 6 c53 100nf c60 100nf c31 220nf c52 330pf r104 20 c109 330pf 15 m3 in1a in1a vl config pwrdn pwr_dn fault tristate thwarn th_warn +3.3v in1b vdd vdd vss vss vccsig vccsig gndreg gndclean in2a in1b in2a in2b protection & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 out1a gnd1a out1a vcc1a 14 12 10 11 out1b gnd1b out1b vcc1b 13 l113 22 h l112 22 h c32 220nf +v cc c108 470nf c31 220nf 7 m17 m15 m16 m14 8 9 out2a gnd2a out2a vcc2a 6 4 2 3 out2b gnd2b d00au1148bbc out2b vcc2b 5 19 31 20 gndsub 1 in2b 32 c110 100nf c111 100nf r103 6 r102 6 8 ? 8 ? 10 h 10 h 100nf film 220nf x7r 220nf x7r 1 f x7r 2200 f 63v 220nf 680nf film 100nf film 100nf 10k 10k 3.3 1/2w 3.3 1/2w 100nf x7r 100nf x7r add. in1a in1a v l config pwrdn npwr_dn fault tristate thwarn th_warn +3.3v 100nf 100nf x7r in1b vdd vdd vss vss vccsig vccsig gndreg gndclean in1b in2a 29 23 n.c. 24 25 27 26 28 30 21 22 33 34 35 36 17 16 18 out1a gnd1b out1a vcc1b 10 13 11 out1b gnd1a out1b 14 vcc 330pf 22 ? 1/2w 4 ? gnd2a 6 2 12 vcc1a 15 vcc2b 4 vcc2a 7 3 out2b gnd2b d04au1545bc out2b 5 19 31 20 gndsub 1 in2b 32 8 9 out2a out2a 1 f x7r vcc 220nf
STA515W package mechanical data doc id 11079 rev 2 11/14 5 package mechanical data the STA515W comes in a 36-pin powersso package with exposed pad down (epd). figure 9 below shows the package outline and ta b l e 9 gives the dimensions. in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 9. powersso36 epd dimensions symbol dimensions in mm dimensions in inches min typ max min typ max a 2.15 - 2.47 0.085 - 0.097 a2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.000 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - f - 2.3 - - 0.091 - g- - 0.10 - - 0.004 h 10.10 - 10.50 0.398 - 0.413 h- - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees l 0.60 - 1.00 0.024 - 0.039 m - 4.30 - - 0.169 - n - - 10 degrees - - 10 degrees o - 1.20 - - 0.047 - q - 0.80 - - 0.031 - s - 2.90 - - 0.114 - t - 3.65 - - 0.144 - u - 1.00 - - 0.039 - x 4.10 - 4.70 0.161 - 0.185 y 6.50 - 7.10 0.256 - 0.280
package mechanical data STA515W 12/14 doc id 11079 rev 2 figure 9. powersso36 epd outline drawing h x 45
STA515W revision history doc id 11079 rev 2 13/14 6 revision history table 10. document revision history date revision changes nov-2004 1 initial release. 27-apr-2010 2 added order code STA515W13tr modified figure 1 on page 2 reconstructed pin list in table 2 on page 3 with information from former table 3 functional pin status updated vlow and vhigh spec in table 6 on page 5 modified figure 3 and figure 4 on page 7 updated applications circuits in figure 7 and figure 8 on page 10
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